"""
Type stubs for the custom machine module.
All I/O is routed through the drv master driver using logical pin/bus encoding.
Logical pins are constructed with MAKE_PIN(chip, n); logical buses with MAKE_BUS(kind, n).
PIN_NONE / BUS_NONE (-1) indicate unavailable pins/buses.
"""
from typing import Callable, Optional, Sequence, Union
# ---------------------------------------------------------------------------
# Pin / bus encoding helpers
# ---------------------------------------------------------------------------
[docs]
def MAKE_PIN(chip: int, n: int) -> int:
"""Encode a logical pin: (PERIPH_chip << 8) | n."""
...
[docs]
def MAKE_BUS(kind: int, n: int) -> int:
"""Encode a logical bus: (BUS_TYPE_kind << 8) | n."""
...
# ---------------------------------------------------------------------------
# Chip IDs (PERIPH_*)
# ---------------------------------------------------------------------------
# ---------------------------------------------------------------------------
# Bus kinds (BUS_TYPE_*)
# ---------------------------------------------------------------------------
[docs]
BUS_UART_SC16IS750: int
# ---------------------------------------------------------------------------
# machine.Pin
# ---------------------------------------------------------------------------
[docs]
class Pin:
def __init__(
self,
id: int,
mode: int = ...,
pull: int = ...,
value: int = ...,
) -> None: ...
[docs]
def value(self, v: int = ...) -> Optional[int]: ...
[docs]
def on(self) -> None: ...
[docs]
def off(self) -> None: ...
[docs]
def irq(
self,
handler: Optional[Callable] = ...,
trigger: int = ...,
hard: bool = ...,
) -> None: ...
# ---------------------------------------------------------------------------
# machine.I2C
# ---------------------------------------------------------------------------
[docs]
class I2C:
def __init__(
self,
id: int,
*,
scl: int = ...,
sda: int = ...,
freq: int = ...,
) -> None: ...
[docs]
def scan(self) -> list[int]: ...
[docs]
def readfrom(self, addr: int, nbytes: int, stop: bool = ...) -> bytes: ...
[docs]
def readfrom_into(
self, addr: int, buf: Union[bytes, bytearray], stop: bool = ...
) -> None: ...
[docs]
def writeto(
self, addr: int, buf: Union[bytes, bytearray], stop: bool = ...
) -> int: ...
[docs]
def writevto(
self, addr: int, vector: Sequence[Union[bytes, bytearray]], stop: bool = ...
) -> int: ...
[docs]
def readfrom_mem(
self, addr: int, memaddr: int, nbytes: int, *, addrsize: int = ...
) -> bytes: ...
[docs]
def readfrom_mem_into(
self, addr: int, memaddr: int, buf: bytearray, *, addrsize: int = ...
) -> None: ...
[docs]
def writeto_mem(
self, addr: int, memaddr: int, buf: Union[bytes, bytearray], *, addrsize: int = ...
) -> None: ...
# ---------------------------------------------------------------------------
# machine.SPI
# ---------------------------------------------------------------------------
[docs]
class SPI:
def __init__(
self,
id: int,
baudrate: int = ...,
*,
polarity: int = ...,
phase: int = ...,
bits: int = ...,
firstbit: int = ...,
) -> None: ...
[docs]
def read(self, nbytes: int, write: int = ...) -> bytes: ...
[docs]
def readinto(self, buf: bytearray, write: int = ...) -> None: ...
[docs]
def write(self, buf: Union[bytes, bytearray]) -> None: ...
[docs]
def write_readinto(
self, write_buf: Union[bytes, bytearray], read_buf: bytearray
) -> None: ...
# ---------------------------------------------------------------------------
# machine.UART
# ---------------------------------------------------------------------------
[docs]
class UART:
def __init__(
self,
id: int,
baudrate: int = ...,
bits: int = ...,
parity: Optional[int] = ...,
stop: int = ...,
*,
tx: int = ...,
rx: int = ...,
txbuf: int = ...,
rxbuf: int = ...,
timeout: int = ...,
timeout_char: int = ...,
invert: int = ...,
flow: int = ...,
) -> None: ...
[docs]
def any(self) -> int: ...
[docs]
def read(self, nbytes: int = ...) -> Optional[bytes]: ...
[docs]
def readinto(self, buf: bytearray, nbytes: int = ...) -> Optional[int]: ...
[docs]
def readline(self) -> Optional[bytes]: ...
[docs]
def write(self, buf: Union[bytes, bytearray]) -> Optional[int]: ...
[docs]
def flush(self) -> None: ...
[docs]
def irq(self, trigger: int, handler: Optional[Callable] = ...) -> None: ...
# ---------------------------------------------------------------------------
# machine.PWM
# ---------------------------------------------------------------------------
[docs]
class PWM:
def __init__(
self,
pin: int,
*,
freq: int = ...,
duty: int = ...,
duty_u16: int = ...,
duty_ns: int = ...,
) -> None: ...
[docs]
def freq(self, value: int = ...) -> Optional[int]: ...
[docs]
def duty(self, value: int = ...) -> Optional[int]: ...
[docs]
def duty_u16(self, value: int = ...) -> Optional[int]: ...
[docs]
def duty_ns(self, value: int = ...) -> Optional[int]: ...
[docs]
def deinit(self) -> None: ...
# ---------------------------------------------------------------------------
# machine.ADC
# ---------------------------------------------------------------------------
[docs]
class ADC:
def __init__(self, pin: int) -> None: ...
[docs]
def read(self) -> int: ...
[docs]
def read_u16(self) -> int: ...
[docs]
def read_uv(self) -> int: ...
# ---------------------------------------------------------------------------
# machine.DAC
# ---------------------------------------------------------------------------
[docs]
class DAC:
def __init__(self, pin: int) -> None: ...
[docs]
def write(self, value: int) -> None:
"""Output voltage. value: 0..255."""
...
[docs]
def deinit(self) -> None: ...
# ---------------------------------------------------------------------------
# machine.I2S
# ---------------------------------------------------------------------------
[docs]
class I2S:
def __init__(
self,
id: int,
*,
sck: int,
ws: int,
sd: int,
mode: int,
bits: int,
format: int,
rate: int,
ibuf: int,
) -> None: ...
[docs]
def readinto(self, buf: bytearray) -> int: ...
[docs]
def write(self, buf: Union[bytes, bytearray]) -> int: ...
[docs]
def deinit(self) -> None: ...
@staticmethod
[docs]
def shift(*, buf: bytearray, bits: int, shift: int) -> None: ...